Method of forming nitride films with high compressive stress for improved PFET device performance

ABSTRACT

A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of a U.S. patentapplication Ser. No. 11/160,705, entitled “METHOD OF FORMING NITRIDEFILMS WITH HIGH COMPRESSIVE STRESS FOR IMPROVED PFET DEVICEPERFORMANCE”, filed on Jul. 6, 2005.

FIELD OF THE INVENTION

This invention relates to the manufacture of advanced semiconductordevices, and particularly to improving charge mobility in highperformance p-type field effect transistors (PFETs) in CMOS integrateddevices.

BACKGROUND OF THE INVENTION

In the field of semiconductor device design, it is known that mechanicalstresses within the device substrate can affect device performance.Stress engineering has come to play an important role in improving theperformance of semiconductor devices. In the case of field-effecttransistors (FETs), stress is applied to the channel region of the FETto cause increased mobility of electrons or holes, which in turn gives asubstantial improvement in device speed. In a typical CMOS integratedcircuit device, both n-type and p-type FETs (NFETs and PFETsrespectively) are used. The stress components for the NFET and PFET in agiven device must be engineered and applied differently, in accordancewith the type of device and whether the direction is longitudinal (onthe same axis as the channel current) or transverse to the channelcurrent. It is known that the best stress design provides tensile stressin both longitudinal and transverse directions in the channel regionunder the gate of the NFET, but longitudinal compressive stress andtransverse tensile stress in the channel region under the gate of thePFET.

FIGS. 1A and 1B schematically illustrate a typical device with thedesired stress arrangement. FIG. 1A is a cross-section view of NFET andPFET gate structures 10, 20 formed on substrate 1 with an isolationregion 15 (generally shallow-trench isolation or STI) between them. TheNFET and PFET gate materials 11, 21 have channel regions 13, 23 beneaththem. FIG. 1B is a plan view of the channel regions with the desiredstresses, where arrows T and C represent tensile stress and compressivestress respectively.

U.S. Pat. No. 6,825,529 to Chidambarrao et al., assigned to one of theassignees of the present invention, describes the use of nitride spacers(12 and 22 in FIG. 1A) with different values of intrinsic stress toobtain the desired longitudinal stresses in the channel regions.According to Chidambarrao et al., it is also known that a nitride layerwith high intrinsic stress, deposited over the completed NFET or PFETdevice, will induce corresponding stress in the channel.

The nitride films used in these techniques are deposited byplasma-enhanced CVD (PECVD). Whether a film has intrinsic tensile stressor compressive stress depends on the details of the deposition process.A number of PECVD processes and tools have been used in attempts tomaximize intrinsic compressive stress in nitride films used in the PFETdevices. At present the greatest compressive stress achievable in PECVDnitride appears to be about −2.6 GPa. There is a need for a processwhich can provide significantly greater intrinsic compressive stress inthe deposited nitride film.

SUMMARY OF THE INVENTION

The present invention addresses the above-described need by providing amethod for making a FET device in which a nitride layer overlies thePFET gate structure, where the nitride layer has a compressive stresswith a magnitude greater than about 2.8 GPa. According to the presentinvention, this is done by depositing the nitride layer using ahigh-density plasma (HDP) process. In the HDP process, the substrate isdisposed on an electrode to which a bias power is supplied. The biaspower is in the range of about 50 W to about 150 W for a 200 mm diametersubstrate, and in the range of about 300 W to about 500 W for a 300 mmdiameter substrate. The bias power is characterized as high-frequencypower, typically supplied by an RF generator at 13.56 MHz. The FETdevice may also include NFET gate structures. A blocking layer isdeposited over the NFET gate structures so that the nitride layeroverlies the blocking layer; after the blocking layer is removed, thenitride layer is not in contact with the NFET gate structures.

According to another aspect of the invention, a process for depositing anitride layer on a workpiece is provided. A precursor gas mixtureincluding silane and nitrogen is provided in a plasma reactor; mainpower is supplied to form a plasma in the reactor, and a bias power, ata frequency lower than that of the main power, is supplied to anelectrode in the reactor on which the workpiece is disposed. Thisprocess results in deposition of a nitride layer having a compressivestress with a magnitude greater than about 2.8 GPa.

According to another aspect of the invention, a FET structure isprovided which includes a PFET gate structure with a nitride layeroverlying the gate structure. The nitride layer has a compressive stresswith a magnitude greater than about 2.8 GPa. The nitride layer has athickness in the range of about 300-2000 Å, depending on the design ofthe gate. The FET structure may also include a NFET gate structure, butthe nitride layer is not in contact therewith.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic illustration in cross-section view of a typicalCMOS device having NFET and PFET gate structures.

FIG. 1B is a schematic illustration in plan view of the gate channels inFIG. 1A, showing the desired longitudinal stress in the NFET and PFETrespectively.

FIG. 2 shows an HDP nitride layer deposited on the PFET structure, inaccordance with an embodiment of the invention.

FIG. 3 schematically illustrates an HDP deposition tool in which highfrequency bias power is applied, in accordance with the invention.

FIG. 4 shows FTIR spectra for three nitride films deposited using PECVD,HDP without high frequency bias, and HDP with 100 W high frequency bias,respectively.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT OF THE INVENTION

In a preferred embodiment of the invention, a nitride film is depositedon a substrate having a PFET device using a high-density plasma (HDP)process. In particular, the HDP nitride deposition process includes highfrequency bias power.

The HDP nitride film 25 is deposited over the substrate 1 on which NFETand PFET gate structures 10, 20 have been formed, as shown in FIG. 2.The NFET gate structure is covered with a blocking layer 24 (e.g.photoresist) before the compressive nitride film is deposited, so thatthe nitride contacts the PFET only. A typical thickness for the nitridefilm 25 is in the range 300-2000 Å. The blocking layer is subsequentlyremoved by any convenient process, so that compressive stress is appliedto the PFET gate structures but not the NFET gate structures.

The processes described below have been implemented in a Novellus SpeedHDP chemical vapor deposition tool from Novellus Systems, Inc. Argon,silane and nitrogen are used as precursor gases, with flow ratestypically 350 sccm, 150 sccm and 600 sccm respectively when 200 mmsubstrates are used, and 230 sccm, 90 sccm and 310 sccm respectivelywhen 300 mm substrates are used. During the deposition process thesubstrate temperature is about 375-400° C. and the gas pressure is lessthan 10 mTorr. The low frequency (LF) power is in the range 1000-2000 Wfor 200 mm substrates and in the range 2500-4000 W for 300 mmsubstrates. The high frequency (HF) bias power is in the range 50-150 Wwhen 200 mm substrates are used, and in the range 300-500 W when 300 mmsubstrates are used. Table 1 shows results of HDP nitride deposition onfive 200 mm wafers with Ar, SiH₄ and N₂ flow rates as given above, witha total power of 1870 watts.

TABLE 1 LF power, HF power, Deposition Temperature, Stress, Wafer wattswatts rate, Å/sec ° C. GPa 1 1870 0 22.6 353 −0.41 2 1770 100 23.8 367−2.8 3 1720 150 24.6 375 −2.5 4 1670 200 24.8 381 −2.4 5 1570 300 24.2390 −2.1

It is understood that the negative sign indicates that the stress iscompressive. It may be seen from Table 1 that the magnitude of stressdepends critically on the high frequency bias power.

FIG. 3 is a schematic illustration of a HDP deposition tool 100employing high frequency bias power. Process gases are introduced intothe chamber through inlets 130. The high-density plasma is induced bythe coils 140 (on the exterior of the dome-shaped chamber cover 160)connected to the low frequency RF generator 150. The substrate 1 isplaced on electrode 110 connected to the high frequency RF generator120. The HF generator 120 operates at the standard frequency of 13.56MHz while the LF generator 150 typically operates at 400 KHz.

A comparison of nitride films formed by PECVD and HDP processes has beenperformed using Fourier transform infrared spectroscopy (FTIR). FTIRspectra for three processes (PECVD, HDP without HF bias, and HDP with100 W HF bias) are shown in FIG. 4. Spectrum 41 represents absorbance ofa PECVD nitride film; spectra 42 and 43 represent absorbance of HDPnitride deposited without HF bias and with 100 W HF bias, respectively.The peaks at about 870 cm⁻¹ represent stretching of Si—N bonds; thedifference in peak heights shows that the HDP nitride films have moreSi—N bonding than PECVD nitride films. A further comparison of filmproperties, based on stress and density measurements in addition toFTIR, appears in Table 2.

TABLE 2 Process, Stress, Density, [NH], [SiH], SiN stretching, NHx/SiNWafer bias power GPa g/cm⁻³ cm⁻³ cm⁻³ normalized stretching 1 PECVD −2.02.69 2.9E+22 8E+20 226 0.067 2 HDP/0 W −0.023 2.82 1.9E+22 — 257 0.040 3HDP/100 W −3.3 2.78 2.4E+22 — 267 0.048

Compared to PECVD films, the HDP nitride films have higher density, moreSi—N bonding, and a lower hydrogen content. In addition, the HDP filmshave lower concentrations of NH and no detectable SiH.

HDP deposited nitride films, which previously were used in semiconductormanufacturing for copper passivation and as etch stops, have thus beenshown to be useful in providing very high compressive stress forperformance enhancement in PFET devices. Compressive stresses of −3.0GPa and greater may be obtained; this is a higher stress level than isavailable using PECVD processes.

While the invention has been described in terms of a specificembodiment, it is evident in view of the foregoing description thatnumerous alternatives, modifications and variations will be apparent tothose skilled in the art. Accordingly, the invention is intended toencompass all such alternatives, modifications and variations which fallwithin the scope and spirit of the invention and the following claims.

1. A field-effect transistor (FET) device comprising: a PFET gatestructure formed on a substrate; and a nitride layer overlying the PFETgate structure, the nitride layer having a compressive stress with amagnitude greater than about 2.8 GPa. wherein the nitride layer has adensity between 2.78 g/cm⁻³ and 2.82 g/cm⁻³; a concentration of NHranging from 1.9×10²² to 2.4×10²²/cm⁻³; and has a lower hydrogen contentand more Si—N bonding than a nitride layer produced by a PECVD process.2. A FET device according to claim 1, further comprising an NFET gatestructure formed on the substrate, wherein the nitride layer is not incontact with the NFET gate structure.
 3. A FET device according to claim1, wherein the nitride layer is formed by a high-density plasma (HDP)chemical vapor deposition process.
 4. A FET device according to claim 1,wherein the nitride layer has a thickness in the range of about 300 Å toabout 2000 Å.
 5. A FET device according to claim 1, wherein the nitridelayer has no detectable SiH.